Veröffentlicht 6. Juni 2024 | Version 0.3
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SpaceWire light IP core with Avalon support

  • 1. ROR icon Graz University of Technology

Beschreibung

The 'spwavl' IP core implements a SpaceWire interface with an Avalon Memory-Mapped (MM) and Streaming (ST) frontend. This facilitates a seamless integration and support for Intel/Altera FPGA synthesis tools.  It is based on the SpaceWire light IP core with AMBA support (spwamba) with all dependencies on grlib removed.

Technical info

From the original 'spwamba' core the DMA controllers, and thus the dependency on grlib, and the frontend AHB interface was removed. In consequence, only the structure of the state machine and the interfacing to the underlying SpaceWire components remained. The resulting code is very similar to the 'spwstream' component. On this basis an Avalon Memory-Mapped interface with a compatible register structure was implemented. As a replacement for the integrated DMA controllers, the in- and outgoing streams were made compatible to the Avalon Streaming (ST) standard. This allows to connect external DMA controllers with an Avalon-ST interface .

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Weitere Details

Verwandte Arbeiten

Is derived from
Software: https://github.com/freecores/spacewire_light (URL)
Is described by
Thesis: 10.3217/8bvh6-py284 (DOI)
Is supplemented by
Software: 10.3217/8wdyv-a4p08 (DOI)